From the EIC: Manufacturing test woes

WITH THE MANUFACTURING CAPACITY of thousands of wafers per week, and thousands of dies per wafer, today's silicon comes out of fab really fast—and furious—sporting device I/Os in the gigabit-per-second range. But it is increasingly going into high-volume and low-cost consumer electronic parts, exhausting the available time and money to test these parts. Little wonder that the 2003 International Technology Roadmap for Semiconductors (ITRS) lists the high-speed interface to ATE as the number one test challenge. To be sure, high-speed differential links have been with the industry in communications ICs for a long time, even as communication links move to 10-Gbps speeds in the short haul (backplanes) and 40 Gbps in the long-haul links. What has changed, however, is the recent proliferation of high-speed serial protocols into diverse (and mainstream) processors, ASICs, and SoCs. It is not uncommon to see ASICs with serial interfaces operating at over 3 Gbps, rapidly approaching over 10 Gbps. These ASICs are driven by serial communications and backplane standards such as PCI Express, RapidIO, and HyperTransport—all of these advancing to over 5 Gbps. Suddenly, a part designed for low-cost manufacturing requires manufacturing test solutions that are still dominated by expensive and time-consuming test equipment designed for at-speed functional testing, diagnosis, and debugging. The situation becomes worse: Many of these devices sport multiple high-speed serial interfaces, requiring multiport ATE solutions. But the same economics requires the manufacturer to minimize manufacturing yield losses from test equipment shortcomings and test inaccuracies. For an industry accustomed to planned equipment upgrades, these changes produce many red brick walls, that is, problems with no known solutions. One of these nasty problems is jitter measurement and analysis in ATE. Jitter measurements must account for and discriminate between deterministic and random jitter. A 10-Gbps digital signal has substantial spectral components at the second and third harmonics. Thus, jitter measurements at very wide bandwidths are necessary. For these measurements, jitter accumulation time is typically too high (at tens of seconds), requiring intelligent clock recovery and handling to make it usable for manufacturing test. To be effective in combating yield loss, the test equipment must accommodate the use of forwarded clock and self-timed data streams that might have drift well in excess of bit duration. Although the concept of multiple bit length channels comes naturally to communication system designers, it is a difficult one for test equipment manufacturers accustomed to synchronous bit spitting in the …